30a232-12 rev. b 6/03 this document contains information on a product that is currently released to production at dpac technologies corp. dpac reserves the right to change products or specifications herein without prior notice. 256 megabit synchronous dram dpsd16mx16tky5 1 advanced components packaging pin names a0-a11 row address: a0-a11 column address: a0-a9 ba0, ba1 bank select address dq0-dq15 data in/data out cas column address strobe ras row address strobe we data write enable dqm0, dqm1 data input/output masks cke clock enable clk system clock cs chip select v cc /v ss power supply/ground v ccq /v ssq data output power/ground nc no connect description: the memory stack? series is a family of interchangeable memory devices. the 256 megabit sdram assembly utilizes the space saving lp-stack? technology to increase memory density. this stack is constructed with two 128mb (16m x 8) sdrams. this 256mb lp-stack? has been designed to fit in the same footprint as the 128mb (16m x 8) sdram tsopii monolithic. this stack allows for system upgrade without electrical or mechanical redesign, providing an alternative low cost memory solution. features: ? electrical characteristics meet semiconductor manufacturers? datasheets ? memory organization: (2) 128mb memory devices. each device arranged as 16m x 8 bits (4m x 8 bits x 4 banks) ? memory stack organization: 16m x 16 bits (4m x 16 bits x 4 banks) ? jedec approved tsopii footprint / non jedec pin assignment (with 1 cs, 1 cke, 2 dqms and dq0-dq15) ? optimized for rdimms ? ipc-a-610, class 2, manufacturing standards ? lead free manufacturing process ? package: 54-pin tsopii stack pin-out diagram 1 33 a8 vcc 1 2 54 vss vccq 3 53 dq8 4 52 vssq dq1 5 51 dq15 vssq 6 50 dq6 dq9 7 49 vccq 8 48 dq14 vccq 9 47 dq10 10 46 vssq dq3 11 45 dq13 vssq 12 44 dq4 dq11 13 43 vccq vcc 14 42 dq12 n.c. 15 41 vss we 16 40 dqm1 cas 17 39 dqm0 ras 18 38 clk cs 19 37 cke ba0 20 36 nc ba1 21 35 a11 a10 22 34 a9 a0 23 32 a7 a1 24 31 a6 a2 25 30 a5 a3 26 29 a4 vcc 27 28 vss dq2 dq0 dq5 dq7 (top view) functional block diagram dqm1 cas we dq0-dq7 dqm0 ras ck clk a0-a11 cke cs ba0-ba1 (4m x 8 bits x 4 banks) 128 mb sdram (4m x 8 bits x 4 banks)
30a232-12 rev. b 6/03 2 dpac technologies products & services for the integration age 7321 lincoln way, garden grove, ca 92841 te l 714 898 0007 fax 714 897 1772 www.dpactech.com nasdaq: dpac ?2003 dpac technologies, all rights reserved. dpac technologies?, memory stack?, system stack?, lp-stack?, cs-stack? are tradem arks of dpac technologies corp. dpsd16mx16tky5 256 megabit synchronous dram mechanical diagram .020 [.51] .0315 [.80] top view side view bottom view end view pin 1 index .502.008 .891 max. [12.75.20] [22.63 max.] .102 max. [2.59 max] lead toe-to-toe per device datasheet inch [mm] end view detail .463 [11.76] typ coplanarity: .004 [.10] from seating plane typ. typ. * contact your sales representative for supplier and manufacturer codes. note: 1. ac parameters of base memory are unchanged from device manufacturers? specifications. 2. dc parameters may be affected by stacking. please refer to application note 53a004-00 for further information. 3. for assembly and inspection procedures, refer to application note 53a001-00. 4. maximum reflow temperature recommendation is 215c. ordering information dp - prefix sd 16m x 16 y5 package memory desig memory type memory module without support logic depth width desig tk stackable tsop synchronous dram supplier -dp supplier code 128 megabit (x8) lvttl based mfr id xx revision memory x blank revision not specified per manufacturer die revision manufacturer code * n 70p2 75p2 75 55 60 70 time xxx cycle 10 08 12 p12 p13 7.5ns (133mhz) cl3 5.5ns (183mhz) cl3 7ns (143mhz) cl3 6ns (166mhz) cl2 7ns (133mhz) cl2 7.5ns (133mhz) cl2 pc100 / cl2 12ns (83mhz) 8ns (125mhz) 10ns (100mhz) pc100 / cl3
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